L2 Cache

What is an L2 Cache?

L2 cache refers to “Level 2” cache. It is a set of memory circuits designed to store recently accessed information that had not been caught by the L1 cache. As it is secondary to the Level 1 cache, the L2 cache is also referred to as secondary cache. It often appears larger than L1 cache and performs at a slightly slower rate.

Function

The L2 cache’s main function is to speed up access to information that had been used already by bridging the processor/memory performance gap. L2 Cache is also used to buffer program instructions and data that the processor is about to access from the memory, thus reducing data access time.

Typical Location

The L2 cache may be placed in the following locations:

  1. On the motherboard or daughterboard that inserts into the motherboard; – L2 caches found on the motherboard are either set in a Card Edge Low Profile (CELP) socket or on a coast module. The latter setting looks like a short SIM and plugs into a coast socket located close to the processor;
  2. On the processor core, either integrated or on-die cache; and
  3. In the same packet or cartridge as the processor, but set separate from the processor core.

Pentium Pro, Pentium II, early Pentium III, and slot A Athlon processors have all used this setting for the L2 cache. Pentium Pro processors have the L2 cache sighted on the processor chip itself, but it is not sighted in the same circuit where the processor and L1 cache are located.

Features

The processor’s bus interface employs a particular transfer standard called burst mode in order to facilitate the speedy transfer of data from the L2 cache to the processor. One burst cycle is composed of 4 data transfers where the first 64 addresses in a series are produced by the address bus.

An L2 cache commonly uses a pipeline burst. This type of synchronous cache pre-fetches memory contents before they are requested. It also pre-fetches pipelining, which allows the access of memory value in the cache at the same time another memory value is accessed in DRAM. These techniques reduce processor wait states.